时钟发生器在片上系统处理器中的应用

书籍目录

ABOUT THE AUTHORPREFACEFOREWORD1.INTRODUCTION1.1 WHAT ARE SYSTEM-ON-A-CHIP PROCESSORS?1.2 ORGANIZATION2.PHASE-LOCKED LOOP FUNDAMENTALS2.1 Introduction2.2 PLL Basics2.3 Continuoas-time Linear Analysis of PLLs2.4 Discrete-time Linear Analysis of PLLs2.5 Nonlinear Locking Behaviour of PLLs2.6 Summary3.LOW-VOLTAGE ANALOG CMOS DESIGN3.1 Introduction3.2 MOS Transistors3.3 Low-Voltage Current Mirrors3.4 Low- Voltage Charge Pumps3.5 Low- Voltage Oscillator Design3.6 Voltage and Current References3.7 Summary4.JITTER ANALYSIS IN PHASE-LOCKED LOOPS4.1 Introduction4.2 Jitter Basics4.3 Jitter in Voltage Controlled Oscillators4.4 Jitter Performance of Closed-Loop PLL System4.5 Coupling Noise Effects on Jitter4.6 Summary5.LOW-JITTER PLL ARCHITECTURES5.1 Introduction5.2 Differential PLL Architecture.5.3 Supply Voltage Regulated PLL Architectures5.4 Adaptive PLL Architectures5.5 Resistorless Loop Filter PLLs5.6 Delay-Locked Loop Frequency Multipliers5.7 Summary6.DIGITAL PLL DESIGN6.1 Introduction6.2 Basic Topology6.3 Z-domain Analysis6.4 Circuit Implementation Issues6.5 Alternate Digital PLL for Clock Generation6.6 Summary7.DSP CLOCK GENERATOR ARCHITECTURES7.1 Introduction7.2 Sampling Clock Requirements for Data Converters7.3 Jitter in Frequency Dividers7.4 Fractional-N PLLs as Clock Generators7.5 Oversampled PLL Topologies7.6 Direct Digital Synthesis with Analog Interpolation7.7 Summary8.DESIGN FOR TESTABILITY IN PLLS8.1 Introduction8.2 Verification of SoC PLLs8.3 Jitter Measurement Techniques8.4 Design for Testability and Self-Test in PLLs8.5 Summary9.CLOCK PARTITIONING AND SKEW CONTROL9.1 Introduction9.2 Clock Distribution Networks in SoCs9.3 Performance Limitations in Clock Networks9.4 Active Skew Management Strategies9.5 Multi-phase Clock Generator9.6 Low-Power Clock Distribution Strategies9.7 Multi-clock Domain Interfacing9.8 SummaryINDEX

编辑推荐

　　Clock Generators for SOC Processors　　This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip（soc）processors．　　This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level．The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops（PLLs）．　　On the circuit level，the discussion includes low-voltage analog design in deep submicron digital CMOS processes，effects of supply noise，substrate noise，as well device noise．On the architectural level，the discussion includes PLLanalysis using continuous-time as well as discrete-time models，linear and nonlirear effects of PLL performance，and detailed analysis of locking behavior．

作者简介

《时钟发生器在片上系统处理器中的应用》针对在SOC芯片上使用的全集成频率合成器的设计，从电路和系统的角度对锁相环的原理和设计进行了分析。特别是在电路层次上，讨论了深亚微米CMOS数字工艺中的低电压模拟电路的设计，有比较大的参考意义。在对锁相环基本工作原理分析的基础之上，《时钟发生器在片上系统处理器中的应用》分析了具体的时钟产生方案和电路设计问题，并进一步讨论了锁相环的应用。《时钟发生器在片上系统处理器中的应用》还包括了PLL可测试性设计的内容。最后还从宏观角度讨论了SOC时钟域的设计。书中包含的大量实际问题分析应该有助于读者更好地理解时钟产生器设计中的核心问题。

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