数字集成电路与嵌入式内核系统可测试性设计

内容概要

Alfred L.Crouch从为美国空军修理气象设备开始其测试生涯。随后，他于肯塔基大学获得了电机工程学士和电机工程学硕士学位。他先后在德州仪器公司、数字装备公司和摩托罗拉公司供职，主要从事可测试性设计、测试自动化及计算机半自动测试。他总共申请了9个美国专利，是一名经验丰富的教员和会议主持者。

书籍目录

PrefaceAcknowledgmentsIntroduction1 Test and Design-for-Test Fundamentals1.1 Introduction to Test and DFT Fundamentals1.1.1 Purpose1.1.2 Introduction to Test,the Test Process,and Design-for-Test1.1.3 Concurrent Test Engineering1.2 The Reasons for Testing1.2.1 Why Test?Why Add Test Logic?1.2.2 Pro and Con Perceptions of DFT1.3 The Definition of Testing1.3.1 What Is Testing?1.3.2 Stimulus1.3.3 Response1.4 Test Measurement Criteria1.4.1 What Is measured?1.4.2 Fault Metric Mathematics1.5 Fault Modeling1.5.1 Physical Defects1.5.2 Fault Modeling1.6 Types of Testing1.6.1 Functional Testing1.6.2 Structural Testing1.6.3 Combinational Exhaustive and Pseudo-Exhaustive Testing1.6.4 Full Exhaustive Testing1.6.5 Test Styles1.7 Manufacturing Test1.7.1 The Manufacturing Test Process1.7.2 Manufacturing Test Load Board1.7.3 Manufacturing Test Program1.8 Using Automatic Test Equipment1.8.1 Automatic Test Equipment1.8.2 ATE Limitations1.8.3 ATE Cost Considerations1.9 Test and Pin Timing1.9.1 Tester and Device Pin Timing1.9.2 Tester Edge Sets1.9.3 Tester Precision and Accuracy1.10 Manufacturing Test Program Components1.10.1 The Pieces and Parts of a Test Program1.10.2 Test Program Optimization1.11 Recommended Reading2 Automatic Test Pattern Generation Fundamentals2.1 Introduction to Automatic Test Pattern Generation2.1.1 Purpose2.1.2 Introduction to Automated Test Pattern Generation2.1.3 The Vector Generation Process Flow2.2 The Reasons for ATPG2.2.1 Why ATPG?2.2.2 Pro and Con Perceptions of ATPG2.3 The Automatic Test Pattern Generation Process2.3.1 Introduction to ATPG2.4 Introducing the Combinational Stuck-At Fault2.4.1 Combinational Stuck-At Faults2.4.2 Combinational Stuck-At Fault Detection2.5 Introducing the Delay Fault2.5.1 Delay faults2.5.2 Delay Fault Detection2.6 Introducing the Current-Based Fault2.6.1 Current-Based Testing2.6.2 Current-Based Testing Detection2.7 Testability and Fault Analysis Methods2.7.1 Why Conduct ATPG Analysis or Testability Analysis?2.7.2 What Types of Testability Analysis Are Available?2.7.3 Fault Effective Circuits2.7.4 Controllability-Observability Analysis2.7.5 Circuit Learning2.8 Fault Masking2.8.1 Causes and Effects of Fault Masking2.8.2 Fault Masking on Various Fault Models2.9 Stuck Fault Equivalence2.9.1 Fault Equivalence Optimization2.9.2 Fault Equivalence Side Effects2.10 Stuck-At ATPG2.10.1 Fault Selection2.10.2 Exercising the Fault2.10.3 Detect Path Sensitization2.11 Transition Delay Fault ATPG2.11.1 Using ATPG with Transition Delay Faults2.11.2 Transition Delay Is a Gross Delay Fault2.12 Path Delay Fault ATPG2.12.1 Path Delay ATPG2.12.2 Robust Fault Detection2.12.3 The Path Delay Design Description2.12.4 Path Enumeration2.13 Current-Based Fault ATPG2.13.1 Current-Based ATPG Algorithms2.14 Combinational versus Sequential ATPG2.14.1 Multiple Cycle Sequential Test Pattern Generation2.14.2 Multiple Time Frame Combinational ATPG2.14.3 Two-Time-Frame ATPG Limitations2.14.4 Cycle-Based ATPG Limitations2.15 Vector Simulation2.15.1 Fault Simulation2.15.2 Simulation for Manufacturing Test2.16 ATPG Vectors2.16.1 Vector Vectors2.16.2 Vector Compaction and Compression2.17 ATPG-Based Design Rules2.17.1 The ATPG Tool“NO”Rules List2.17.2 Exceptions to the Rules2.18 Selecting an ATPG Tool2.18.1 The Measurables2.18.2 The ATPG Benchmark Process2.19 ATPG Fundamentals Summary2.19.1 Establishing an ATPG Methodology2.20 Recommended Reading3 Scan Architectures and Techniques3.1 Introduction to Scan-Based Testing3.1.1 Purpose3.1.2 The Testing Problem3.1.3 Scan Testing3.1.4 Scan Testing Misconceptions3.2 Functional Testing3.3 The Scan Effective Circuit3.4 The Mux-D Style Scan Flip-Flops3.4.1 The Multiplexed-D Flip-Flop Scan Cell3.4.2 Perceived Silicon Impact of the Mux-D Scan Flip-Flop3.4.3 Other Types of Scan Flip-Flops3.4.4 Mixing Scan Styles3.5 Preferred Mux-D Scan Flip-Flops3.5.1 Operation Priority of the Multiplexed-D Flip-Flop Scan Cell3.5.2 The Mux-D Flip-Flop Family3.6 The Scan Shift Register or Scan Chain3.6.1 The Scan Architecture for Test3.6.2 The Scan Shift Register(a.k.a The Scan Chain)3.7 Scan Cell Operations3.7.1 Scan Cell Transfer Functions3.8 Scan Test Sequencing3.9 Scan Test Timing3.10 Safe Scan Shifting3.11 Safe Scan Sampling:Contention-Free Vectors3.11.1 Contention-Free Vectors3.12 Partial Scan3.12.1 Scan Testing with Partial-Scan3.12.2 Sequential ATPG3.13 Multiple Scan Chains3.13.1 Advantages of Multiple Scan Chains3.13.2 Balanced Scan Chains3.14 The Borrowed Scan Interface3.14.1 Setting up a Borrowed Scan Interface3.14.2 The Shared Scan Input Interface3.14.3 The Shared Scan Output Interface3.15 Clocking,On-Chip Clock Sources,and Scan3.15.1 On-Chip Clock Sources and Scan Testing3.15.2 On-Chip Clocks and Being Scan Tested3.16 Scan-Based Design Rules3.16.1 Scan-Based DFT and Design Rules3.16.2 The Rules3.17 Stuck-At(DC)Scan Insertiion3.17.1 DC Scan Insertion3.17.2 Extras3.17.3 DC Scan Insertion and Multiple Clock Domains3.18 Stuck-At Scan Diagnostics3.18.1 Implementing Stuck-At Scan Diagnostics3.18.2 Diagnostic Fault Simulation3.18.3 functional Scan-Out3.19 At-Speed Scan(AC)Test Goals3.19.1 AC Test Goals3.19.2 Cost Drivers3.20 At-Speed Scan Testing3.20.1 Uses of At-Speed Scan Testing3.20.2 At-Speed Scan Sequence3.20.3 At-Speed Scan versus DC Scan3.21 The At-Speed Scan versus DC Scan3.21.1 At-Speed Scan Interface3.21.2 At-Speed“Safe Shifting”Logic3.21.3 At-Speed Scan Sample Architecture3.22 The At-Speed Scan Interface3.22.1 At-Speed Scan Shift Interface3.22.2 At-Speed Scan Sample Interface3.23 Multiple Clock and Scan Domain Operation3.23.1 Multiple Timing Domains3.24 Scan Insertion and Clock Skew3.24.1 Multiple Clock Domains,Clock Skew,and Scan Insertion3.24.2 Multiple Time Domain Scan Insertion3.25 Scan Insertion for At-Speed Scan3.25.1 Scan Cell Substitution3.25.2 Scan Control Signal Insertion3.25.3 Scan Interface Insertion3.25.4 Other Considerations3.26 Critical Paths for At-Speed Scan3.26.1 Critical Paths3.26.2 Critical Path Selection3.26.3 Path Filtering3.26.4 False Path Content3.26.5 Real Critical Paths3.26.6 Critical Path Scan-Based Diagnostics3.27 Scan-Based Logic BIST3.27.1 Pseudo-Random Pattern Generation3.27.2 Signature Analysis3.27.3 Logic Built-In Self-Test3.27.4 LFSR Science(A Quick Tutorial)3.27.5 X-Management3.27.6 Aliasing3.28 Scan Test Fundamentals Summary3.29 Recommended Reding4 Memory Test Architectures and Techniques4.1 Introduction to Memory Testing4.1.1 Purpose4.1.2 Introduction to Memory Test4.2 Types of Memories4.2.1 Categorizing Memory Types4.3 Memory Organization4.3.1 Types of Memory Organization4.4 Memory Design Concerns4.4.1 Trade-Offs in Memory Design4.5 Memory Integration Concerns4.5.1 Key Issues in Memory Integration4.6 Embedded Memory Testing Methods4.6.1 Memory Test Methods and Options4.7 The Basic Memory Testing Model4.7.1 Memory Testing4.7.2 Memory Test Fault Model4.7.3 Memory Test Failure Modes4.8 The Stuck-At Bit-Cell Based Fault Models4.8.1 Stuck-At Based Memory Bit-Cell Fault Models4.8.2 Stuck-At Fault Exercising and Detection4.9 The Bridging Defect-Based Fault Models4.9.1 Bridging Defect-Based Memory Test Fault Models4.9.2 Linking Defect Memory Test Fault Models4.9.3 Bridging Fault Exercising and Detection4.10 The Decode Fault Model4.10.1 Memory Decode Fault Models4.10.2 Decode Fault Exercising and Detection4.11 The Data Retention Fault4.11.1 Memory Test Data Retention Fault Models4.11.2 DRAM Refresh Requirements4.12 Diagnostic Bit Mapping4.12.1 Memory Test Diagnostics:Bit Mapping4.13 Algorithmic Test Generation4.13.1 Introduction to Algorithmic Test Generation4.13.2 Automatic Test Generation4.13.3 BIST-Based Algorithmic Testing4.14 Memory Interaction with Scan Testing4.14.1 Scan Test Considerations4.14.2 Memory Interaction Methods4.14.3 nput Observation4.14.4 Output Control4.15 Scan Test Memory Modeling4.15.1 Modeling the Memory for ATPG Purposes4.15.2 Limitations4.16 Scan Test Memory Black-Boxing4.16.1 The Memory Black-Boxing Technique4.16.2 Limitations and Concerns4.17 Scan Test Memory Transparency4.17.1 The Memory Transparency Technique4.17.2 Limitations and Concerns4.18 Scan Test Memory Model of The Fake Word4.18.1 The Fake Word Technique4.18.2 Limitations and Concerns4.19 Memory Test Requirements for MBIST4.19.1 Memory Test Organization4.20 Memory Built-In Self-Test Requirements4.20.1 Overview of Memory BIST Requirements4.20.2 At-Speed Operation4.21 An Example Memory BIST4.21.1 A Memory Built-In Self-Test4.21.2 Optional Operation4.21.3 An Example Memory Built-In Seft-Test4.22 MBIST Chip Integration Issues4.22.1 Integrating Memory BIST4.23 MBIST Integrating Memory BIST4.23.1 MBIST Default Operation4.24 MBIST Power Concerns4.24.1 Banked Operation4.25 MBIST Design-Using LFSRs4.25.1 Pseudo-Radnom Pattern Generation for Memory Testing4.25.2 Signature Analysis and Memory Teting4.25.3 Signature Analysis and Diagnostics4.26 Shift-Based Memory BIST4.26.1 Shift-Based Memory Testing4.26.2 Output Assessment4.27 ROM BIST4.27.1 Purpose and Function of ROM BIST4.27.2 The ROM BIST Algorithm4.27.3 ROM MISR Selection4.27.4 Signature Compare Method4.28 Memory Test Summary4.29 Recommended Reading5 Embedded Core Test Fundamentals5.1 Introduction to Embedded Core Testing5.1.1 Purpose5.1.2 Introduction to Embedded Core-Based Chip Testing5.1.3 Reuse Cores5.1.4 Chip Assembly Using Reuse Cores5.2 What Is a Core?5.2.1 Defining Core?5.2.2 The Core DFT and Test Problem5.2.3 Built-In DFT5.3 What is Core-Based Design?5.3.1 Design of a Core-Based Chip5.3.2 Core-Based Design Fundamentals5.4 Reuse Core Deliverables5.4.1 Embedded Core Deliverables5.5 Core DFT Issues5.5.1 Embedded Core-Based Design Test Issues5.6 Development of a ReUsable Core5.6.1 Embedded Core Considerations for DFT5.7 DFT Interface Considerations-Test Signals5.7.1 Embedded Core Interface Considerations for DFT-Test Signals5.8 Core DFT Interface Concerns-Test Access5.8.1 Test Access to the Core Interface5.9 DFT Interface Concerns-Test Wrappers5.9.1 The Test Wrapper as a Signal reduction Element5.9.2 The Test Wrapper as a Frequency Interface5.9.3 The Test Wrapper as a Virtual Test Socket5.10 The Registered Isolation Test Wrapper5.11 The Slice Isolation Test Wrapper5.12 The Isolation Test Wrapper-Slice Cell5.13 The Isolation Test Wrapper-Core DFT Interface5.14 Core test Mode Default Values5.14.1 Internal versus External Test Quiescence Defaults Application5.15 DFT Interface Wrapper Concerns5.15.1 Lack of Bidirectional Signals5.15.2 Test Clock Source Considerations5.16 DFT Interface Concerns-Test Frequency5.16.1 Embedded Core Interface Concerns for DFT-Test Frequency5.16.2 Solving the Frequency Problem5.17 Core DFT Development5.17.1 Internal Parallel Scan5.17.2 Wrapper Parallel Scan5.17.3 Embedded Memory BIST5.17.4 Other DFT Features5.18 Core Test Economics5.18.1 Core DFT,Vectors,and Test Economics5.18.2 Core Selection with Consideration to DFT Economics5.19 Chip Design with a Core5.19.1 Elements of a Core-Based Chip5.19.2 Embedded Core Integration Concerns5.19.3 Chip-Level DFT5.20 Scan Testing the Isolated Core5.21 Scan Testing the Non-Core Logic5.21.1 Scan Testing the Non-Core Logic in Isolation5.21.2 Chip-Level Testing and Tester Edge Sets5.22 User Defined Logic Chip-Level DFT Concerns5.23 Memory Testing with BIST5.24 Chip-Level DFT Integration Requirements5.24.1 Embedded Core-Based DFT Integration Architecture5.24.2 Physical Concerns5.25 Embedded Test Programs5.26 Selecting or Receiving a Core5.27 Embedded Core DFT Summary5.28 Recommended ReadingAbout the CDGlossary of TermsIndexAbout the Author

作者简介

书中包括的索引使你能够根据自己的需要，直接阅读你所关注的内容。主要内容包括：设计核心，关注嵌入核心和嵌入存储器；系统集成和超大规模集成电路的设计问题；AC扫描、正常速度扫描和嵌入式可测试性设计；内建、自测试、含内存BIST、逻辑BIST及扫描BIST；虚拟测试套接字和隔离测试

·重用设计，包括重用和隔离测试；用VSIA和IEEE P1500标准处理测试问题。

   书中穿插的整幅图解直接来自作者的教学材料。通过为书中的第一部分列出流程图、工程图表和内容接要，使得读者能够更快更容易地学习和查找。本书是与设计和测试工作相关的工程师和管理员所备的资料书籍。

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