Verilong数字系统设计

书籍目录

Chapter 1　Digital System Design Automation with Verilog　1.1　Digital Design Flow　1.2　Verilog HDL 　1.3　Summary　Problems　Suggested ReadingChapter 2　Register Transfer Level Design with Verilog　2.1　RT Level Design　2.2　Elements of Verilog　2.3　Component Description in Verilog　2.4　Testbenches　2.5　Summary 　Problems　Suggested ReadingChapter 3　Verilog Language Concepts　3.1　Characterizing Hardware Languages　3.2　Module Basics　3.3　Verilog Simulation Model　3.4　Compiler Directives　3.5　System Tasks and Functions　3.6　Summary　Problems　Suggested ReadingChapter 4　Combinational Circuit Description　4.1　Module Wires　4.2　Gate Level Logic　4.3　Hierarchical Structures　4.4　Describing Expressions with Assign Statements　4.5　Behavioral Combinational Descriptions　4.6　Combinational Synthesis　4.7　Summary　Problems　Suggested ReadingChapter 5　Sequetial Circuit Description　5.1　Sequential Models　5.2　Basic Memory Components　5.3　Functional Registers　5.4　State Machine Coding　5.5　Sequential Synthesis　5.6　Summary　Problems　Suggested ReadingChapter 6　Component Test Verification　6.1　Testbench　6.2　Testbench Techniques　6.3　Design Verification　6.4　Assertion Verification　6.5　Text Based Testbenches　6.6　Summary　Problems　Suggested ReadingChapter 7　Detailed Modeling　7.1　Switch Level Modeling　7.2　Strength Modeling　7.3　Summary　Problems　Suggested ReadingChapter 8　RT Level Design and Test　8.1　Sequential Multiplier　8.2　von Neumann Computer Model　8.3　CPU Design and Test　8.4　Summary　Problems　Suggested Reading Appendix A　List of KeywordsAppendix B　Frequently Used Syetem Taske and FunctionsAppendix C　Compiler DirectivesAppendix D　Verilog Formal Syntax DefinitionAppendix E　Verilog Assertion Monitors

作者简介

本书主要讲述基于IEEE Std 1364-2001版本的Verilog硬件描述语言，着重讲述了使用Verilog进行数字系统的设计、验证及综合。根据数字集成电路设计的工程需求，本书重点关注了testbench的设计编写、验证和测试技术，深入讲述了基于Verilog HDL的开关级、门级、RTL级、行为级和系统级建模技术，从而使读者能尽快掌握硬件电路和系统的高效Verilog编程技术。书中把RTL描述、电路综合和testbench验证测试技术紧密结合，给出了多个从设计描述到验证的RTL数字电路模块和系统的设计实例。改编者在对标题、重点句子和段落进行注解时，在翻译的基础上针对较难理解的内容做了详细说明。本书为英文版。

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